Full description

CD40174BE same as HEF40174B

hex edge-triggered D-type flip-flop with six data inputs (D0 to D5), a clock input (CP), an overriding asynchronous master reset input (MR), and six buffered outputs (Q0 to Q5). Information on D0 to D5 is transferred to Q0 to Q5 on the LOW-to-HIGH transition of CP if MR is HIGH. When LOW, MR resets all flip-flops (Q0 to Q5 = LOW) independent of CP and D0 to D5.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD , VSS, or another input.